The software between AI and silicon
We ship compilers and AI software stacks on production ARM silicon today — and we're building the same depth into the RISC-V architectures defining the next generation of AI.
15+ years
compiler and architecture expertise
10+ RISC‑V extensions
enabled through upstream toolchains
Multiple leadership roles
in RISC‑V International
Multiple core contributors
to GCC, LLVM, QEMU, and Linux
Industry Leadership
Roles in global semiconductor and RISC‑V initiatives
Upstream Authority
Core contributors to GCC, LLVM, and Linux
Silicon Enablement
Supporting emerging CPU and accelerator architectures
Deep Expertise
Decades of compiler and architecture experience
Ecosystem Builders
From silicon to production software
AI / ML
PyTorch, TensorFlow, and ONNX Runtime — tuned for custom silicon, not generic builds
Datacenter & Enterprise
High-throughput compilers and optimised runtimes for server-class RISC‑V and ARM
Embedded & Edge
Inference on milliwatt budgets — from microcontrollers to smart sensors
We define the instructions before the silicon is committed. ISA extensions for matrix operations, inference pipelines, and AI acceleration — profiled against real workloads, validated in real compilers, and pushed through the standards process to ratification.
GCC and LLVM backends across ARM and RISC‑V. Code generation for custom AI extensions. Auto-vectorisation that actually works. If your silicon has a capability, we make sure the compiler knows about it — and uses it.
PyTorch, TensorFlow, ONNX Runtime — tuned for your hardware, not generic builds. We've shipped production AI stacks on ARM and we build them from scratch on RISC‑V. From kernel bring-up to framework integration, we close the gap between silicon and the models that run on it.
The same engineers who define the matrix-computing extensions write the compilers that target them and build the software ecosystem for adoption. That's not a service portfolio — it's a feedback loop. Every layer informs the others. We were the first to call RISC-V the AI-native architecture. We've been shipping on that ever since.
Becoming the Human in the Loop
AI-assisted engineering changes who wins in deep tech — and it's not who most people think. The throughput gains are real, but only when architect-level engineers are steering. Speed without judgement is an unguided missile.
Makeljana Shkurti
Now Comes the Hard Part.
A compelling architecture and a production-ready platform are two entirely different things. The distance between them is where most of the honest work still needs to happen.
Makeljana Shkurti
And what the Zicond ISA extension does about it
A missing instruction in RISC‑V created a class of problems where branch direction determines register allocation quality. Two instructions eliminate the entire problem.
Philipp Tomsich
Tell us where performance is being left on the table — or where the software stack doesn’t exist yet. RISC-V, ARM, AI, HPC. We’ll find the cycles your compiler is missing.
Tell us about your silicon and what needs to ship with it. Compilers, AI frameworks, platform enablement — we’ll scope what matters and move fast.
The ISA extension that needs a compiler backend. The AI workload that won’t vectorise. The silicon that needs a software ecosystem before it can ship. That’s what we do.
Tell us where your silicon is underperforming — or where the software stack doesn’t exist yet. RISC-V, ARM, AI, HPC. We’ll scope it together.
Or email us directly at inquiries@vrull.eu
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You can also reach us at inquiries@vrull.eu